This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-129908, filed Apr. 26, 2001; and No. 2001-201280, filed Jul. 2, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a gate structure of an MOS transistor, for example, for use in a dynamic memory integrated circuit.
2. Description of the Related Art
In recent years, for the purpose of suppressing a short channel effect, reducing power consumption and enhancing a driving power, various types of MOS transistors structures such as a double gate type MOS transistor and a surround gate type MOS transistor have been proposed.
FIG. 44 shows a conventional MOS transistor of a double gate structure described in IEDM 97 427-430.
In FIG. 44, reference numeral 211 denotes a drain region in a semiconductor substrate, 212 denotes a source region in the semiconductor substrate, 213 denotes a top gate provided in the upper portion of the semiconductor substrate in a horizontal direction, 214 denotes a bottom gate provided in the lower portion of the semiconductor substrate in the horizontal direction, 215 denotes a channel region in the semiconductor substrate sandwiched between the top gate and the bottom gate, and 216 denotes a gate insulating film for insulating the top gate 213 and the bottom gate 214 from the drain region 211, the source region 212, and the channel region 215.
In the MOS transistor, the top gate 213 and the bottom gate 214 are provided in the upper portion and the lower portion of the semiconductor substrate in the horizontal direction, the channel region 215 is provided between the top gate 213 and the bottom gate 214, thereby to provide a MOS transistor having a double gate structure.
In the MOS transistor having the double gate structure, the bottom gate 214 is positioned just under the top gate 213 and thus functions as a back gate. Therefore, the channel region 215 is depleted, the short channel effect is reduced, the drivability is enhanced, and other effects can be expected.
However, in this case, after forming the back gate 214 and the gate insulating film 216 on the surface of the back gate 214, a single-crystal layer has to be formed as an element region of the MOS transistor. However, the process forming the layer is complex, and it is difficult to enhance the reliability of the device.
FIG. 45 shows another conventional example of the MOS transistor having the double gate structure.
In FIG. 45, reference numeral 221 denotes a drain region in a semiconductor substrate, 222 denotes a source region in the semiconductor substrate, 223 denotes a top gate provided in a vertical direction in the semiconductor substrate, 224 denotes a bottom gate provided in the vertical direction in the semiconductor substrate, 225 denotes a channel region in the semiconductor substrate provided between the top gate 223 and the bottom gate 224, and a gate insulating film (not shown) for insulating the top gate 223 and the bottom gate 224 from the drain region 221, source region 222, and the channel region 225 is formed.
In the MOS transistor of this example, the top gate 223 is provided on the left side in the semiconductor substrate in the vertical direction, the bottom gate 224 is provided on the right sides in the semiconductor substrate in the vertical direction, the channel region 225 is sandwiched between the top gate 223 and the bottom gate 224, thereby forming a MOS transistor having a double gate structure.
However, in this MOS transistor of the double gate structure, it is necessary to process the gates on a step portion, and to vertically introduce impurities, and thus the forming process is complex.
With the conventional MOS transistors as described above, the forming process is complex. In this point of view, there has been a demand for the structure of the MOS transistor which can be realized with a relatively easy processing method and which can provide advantages similar to those effected by the double gate type MOS transistor.
Also, in recent years, various types of DRAMS in which one transistor is used as a memory cell have been proposed as follows.
(1) JOHN E. LEISS et al., xe2x80x9cDRAM Design using the Taper-Isolated Dynamic Cellxe2x80x9d (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 2 APRIL. 1982, pp 337-344)
(2) Jpn. Pat. Appln. KOKAI Publication No. 1991-171768
(3) Marnix R. Tack et al., xe2x80x9cThe Multistable Charge-Controlled Memory Effect in SOI MOS transistors at Low Temperaturesxe2x80x9d (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 37, MAY, 1990, pp 1373-1382)
(4) Hsing-jen Wann et al., xe2x80x9cA Capacitorless DRAM Cell on SOI Substratexe2x80x9d (IEDM 93, pp 635-638)
A memory cell of (1) is constituted of a MOS transistor having an embedded channel structure. A parasitic transistor formed on a taper portion of an element isolating insulation film is used to charge or discharge a surface reverse layer, and binary data is stored in accordance with the charge or discharge.
In a memory cell of (2), a well-separated MOS transistor is used, and a threshold value determined by a well potential of the MOS transistor is stored as the binary data.
A memory cell of (3) is constituted of the MOS transistor on an SOI substrate. A hole accumulation in an interface portion generated by applying a large negative voltage from the side of the SOI substrate is utilized, and the binary data is stored in accordance with the charge or discharge of the hole.
A memory cell of (4) is constituted of the MOS transistor formed on the SOI substrate. One MOS transistor is provided in the structure. However, a reverse conductivity layer is superposed upon the surface of the drain diffusion layer so that the substantial structure is such that a writing PMOS transistor and a reading NMOS transistor are substantially combined. The substrate region of the NMOS transistor is used as a floating node, and the binary data is stored in accordance with the potential.
However, in (1), the structure is complicated, and there is a problem in controllability of properties, because the parasitic transistor is used. In (2), the structure is simple, however it is necessary to connect both drain and source to a signal line and control the potential. Moreover, because of the well isolation, a cell size is large, and the data cannot be rewritten for each bit. In (3), it is necessary to control the potential from the SOI substrate side, the data cannot be rewritten for each bit, and there is a problem in controllability. In (4), a unique transistor structure is necessary, the memory cell requires a word line, write bit line, read bit line, and purge bit line, and hence the number of signal lines increases.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; drain and source regions of a MOS transistor formed in a surface of the semiconductor substrate; a gate electrode formed on a surface of a channel region of the MOS transistor between the drain and source regions of the semiconductor substrate with a gate insulating film between the gate electrode and the channel region; and trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, characterized by further comprising a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.
According to another aspect of the present invention, there is provided a semiconductor device comprising: an SOI semiconductor substrate in which a silicon layer is formed on an insulating film formed on a supporting semiconductor substrate; drain and source regions of a MOS transistor formed in a surface of the SOI semiconductor substrate; a gate electrode formed on a surface of a channel region of the MOS transistor between the drain and source regions of the semi-conductor substrate with a gate insulating film between the gate electrode and the channel region; and trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate; characterized by further comprising a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor; a well region formed in a surface of the supporting semiconductor substrate of the SOI semiconductor substrate, a lower end of the conductive material layer being connected to the well region, and the upper portion of the conductive material layer being covered with the insulating film formed on the surface of the element isolation region.
According to a further aspect of the present invention, there is provided a semiconductor device comprising: a memory cell array including an arrangement of MOS transistors for memory cells formed on a semiconductor substrate; a peripheral circuit region formed on the semiconductor substrate; and a plurality of trench type element isolation regions formed in the memory cell array and the peripheral circuit region, the element isolation regions having trenches formed in a surface of the semiconductor substrate, characterized by further comprising a conductive material layer for a back gate electrode, which is embedded in the trench at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under a channel region of the MOS transistor or to voltage-control the semiconductor substrate region.
According to a further aspect of the present invention, there is provided a semiconductor memory device characterized by comprising a vertical MOS transistor including: a semiconductor substrate; a first conductive type element region defined in the semiconductor substrate, the element region constituting a channel region; first and second gate electrodes embedded in first and second trenches formed to sandwich the element region, the first and second gate electrodes opposing to side surfaces of the element region; first and second gate insulation films provided between the first gate electrode and the element region and the second gate electrode and the element region, respectively; a second conductive type drain diffusion layer formed on a surface of the element region; and a second conductive type source diffusion layer embedded in semiconductor substrate in a predetermined depth.
According to a further aspect of the present invention, there is provided a manufacturing method of a semiconductor memory device, characterized by comprising: forming an element forming region defined by an element isolation insulating film in a semi-conductor substrate; ion-implanting impurities in the semiconductor substrate; forming a source diffusion layer adjacent to a bottom of the element forming region; forming at least two trenches at a pre-determined distance in the element forming region; forming gate insulating films on side surfaces of an element channel region sandwiched by the two trenches; embedding first and second gate electrodes in the trenches; and forming a drain diffusion layer on the surface of the element channel region.